In recent years, owing to advances in microfabrication technologies in the manufacture of semiconductor devices, the miniaturization of fabrication patterns is remarkable, raising a need for large-magnification measurement in inspection and measurement processes in the semiconductor production. Especially, in semiconductor fabrication processes, various kinds of resolution enhancement technology (RET) are employed to perform per-layer process treatment, such as advanced exposure and etching or the like; then, superposition with the next layer is performed to form circuit patterns sequentially.
Management of the superposition in this case is done by means of an optical testing/inspection device using dedicated alignment marks.
More specifically, although dedicated patterns for superposition are disposed in the periphery (e.g., at four corners) of a shot area, which is a unit of exposure, for management of a superposition situation of this shape by using an optical inspection device, high-accuracy superposition management is important in order to realize high yields, resulting in optics-based management approaching its limit.
Additionally, in optical scheme-based systems, there are cases where the superposition measurement experiences an error increase due to the influence of transfer-pattern distortions caused by the lens aberration of an exposure device. To cope with this, it becomes necessary to exclude the lens aberration-based error factors by execution of superposition measurement of fine patterns in local regions.
Patent Literature 1 discloses a technique for measuring dimensions between patterns belonging to a plurality of layers. According to the measurement method disclosed in Patent Literature 1, it is possible to perform it by using an image representing the actually formed “real” patterns. Thus, it is possible to measure inter-pattern dimensions with very high accuracy.